1. Field of the Invention
The present invention relates to an input buffer circuit, and more particularly, to an input buffer circuit which provides a signal interface environment between chips having different voltage domains and a gate driver Integrated Circuit (IC) including the input buffer circuit.
2. Description of the Related Art
A flat panel display device displays an image using a flat display panel like an LCD, an LED, and an OLED.
For example, an LCD requires a gate driving signal and a source driving signal in order to display an image. An LCD includes an LCD panel for displaying an image, a gate driver IC for providing a gate driving signal to the LCD panel, a source driver IC for providing a source driving signal to the LCD panel, and a timing controller for providing a gate signal and a control signal to the gate driver IC and a source signal and a control signal to the source driver IC.
Most semiconductor parts mounted on a flat panel display device adopt various aspects of techniques for reducing consumption power. For example, an LCD can be driven according to a low-voltage driving method in order to reduce consumption power.
In order for an LCD to be driven according to the low-voltage driving method, the timing controller or the source driver IC fabricated by a low-voltage process is mounted on the LCD. The low-voltage process means a manufacture process of forming elements designed to operate in response to an operating voltage of a low-voltage domain.
In contrast, the gate driver IC is fabricated by a high-voltage process due to an operating characteristic in which the LCD panel is driven by high voltage. The high-voltage process means a manufacture process of forming elements designed to operate in response to an operating voltage of a high-voltage domain that is higher than a low-voltage domain.
For example, the timing controller or the source driver IC can be designed and fabricated to operate in a low-voltage domain having an operating voltage of 1.8 V to 2.0 V, and the gate driver IC can be designed and fabricated to operate in a high-voltage domain having an operating voltage of 3.3 V to 6 V.
If signals need to be transmitted and received between chips having different voltage domains used in driving, in general, a signal is converted into a voltage level suitable for a voltage domain of a chip that receives a signal to be transmitted by a chip that will send the signal.
In the case of the timing controller and the gate driver IC, the timing controller driven in a low-voltage domain is configured to convert the gate signal suitably for a high-voltage domain and to output the converted signal so that the converted signal can be recognized by the gate driver IC that is driven in a high-voltage domain. That is, the timing controller requires an additional circuit for converting the gate signal, internally generated in a low-voltage domain, suitably for a high-voltage domain and outputting the converted signal. Accordingly, there is a problem in that the chip size is increased by the size of the additional circuit configured in the timing controller.
As described above, the size of a chip that sends a signal is increased by the size of an additional circuit configured to solve a signal interface.